Spmi Interface

stands for System Power Management Interface .

Note: Unlike I²C, SPMI lines typically do not require external pull-up resistors on modern implementations; the controllers often use push-pull drivers or active pull-ups to achieve higher speeds. spmi interface

&spmi0 pm8998@0 compatible = "qcom,pm8998"; reg = <0x0 SPMI_USID>; pm8998_pon: pon@800 reg = <0x800>; compatible = "qcom,pm8916-pon"; ; ; ; stands for System Power Management Interface

| Feature | I²C | SPMI | | :--- | :--- | :--- | | | General purpose sensors, RTC, EEPROMs. | Power management (PMICs), regulators. | | Speed | Up to 1 MHz (Fast Mode Plus). | Up to 26 MHz. | | Addressing | 7-bit or 10-bit. | 4-bit (up to 16 devices per bus). | | Handshake | No hardware flow control. | Supports "Handshake" and "Park" modes for flow control. | | Command Structure | Simple read/write. | Complex commands (Read, Write, Ext_Write, Ext_Read, Reset, Sleep). | | Power Efficiency | Good. | Optimized (features specific sleep/wake commands). | | Power management (PMICs), regulators

| Feature | SPMI | I²C | SBI (SSBI) (Legacy) | | ---------------- | ---------------------------------- | --------------------------- | ---------------------------- | | | PMIC control (mobile/embedded) | General purpose sensors, EEPROM | Legacy Qualcomm PMIC control | | Speed (max) | 26 MHz | 5 MHz (Fast Mode Plus) | ~4.8 MHz | | Multi-Master | Yes | Yes | No | | Slave Address | 4 or 8-bit | 7 or 10-bit | Fixed (one slave) | | Error Checking | Parity + CRC (optional) | None (only basic ACK/NACK) | None | | Power | Low Power + High Speed modes | Single mode (often fixed) | Single mode | | Complexity | Medium (more than I²C) | Low | Very Low |

SPMI is a command/response protocol. A transaction always consists of: