A bidirectional, half-duplex data line used by both masters and slaves to transmit command sequences, addresses, payloads, and handshakes. Topology and Device Capacity A single shared SPMI bus can scale up to support:
An SPMI transaction is built around and responses . The fundamental unit is the frame , and multiple frames form a sequence. spmi bus
The SPMI bus protocol is a master-slave protocol, where a master device initiates transactions and a slave device responds to these transactions. The protocol consists of the following steps: A bidirectional, half-duplex data line used by both
Typically integrated into the core processing units or SoCs. pmic@0 compatible = "qcom
&spmi0 status = "okay"; pmic@0 compatible = "qcom,pm8998"; reg = <0x0 SPMI_USID>; regulators smpc_1: smpc1 regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1150000>; ; ; ; ;