"Preset 3... no. Preset 5," he muttered. "Come on, PAM-4. Talk to me."
Technical Standards Research Unit Disclaimer: This report does not contain the proprietary PDF content but summarizes publicly known features and access rules for the PCIe 6.0 specification.
The console flickered.
Because PAM4 packs four voltage levels into the same voltage swing as NRZ, the vertical separation between levels is reduced, leading to higher noise sensitivity.
"We’re treating this like 5.0," Elias realized aloud. "We’re assuming the signal is robust enough to survive a little noise. But with PAM-4, the voltage levels are closer together. A tiny ripple that 5.0 would ignore? That’s a data corruption event for 6.0." pcie base specification 6.0 pdf
He scrolled through the PDF on his second monitor, his eyes scanning the complex diagrams. The culprit had to be PAM-4 encoding. That was the big shift in the 6.0 spec. Moving from NRZ (Non-Return-to-Zero), which was a simple on/off switch, to PAM-4 (Pulse Amplitude Modulation 4-level), which used four distinct voltage levels to encode two bits of data per clock cycle.
"Sarah, what's the length of the trace from the CPU to the slot?" "Preset 3
It was elegant on paper. In practice, it was a nightmare.