assign product = a * b;
In Verilog, this can be implemented using a generate loop: multiplier in verilog
always @(posedge clk) begin if (i == 8'd0) begin multiplier <= b; multiplicand <= a; product <= 16'd0; end else begin product <= product + multiplicand; multiplier <= multiplier - 1'b1; end i <= i + 1'b1; end assign product = a * b; In Verilog,
always @(a, b) begin multiplicand <= a; multiplier <= b; product <= 16'd0; state <= 2'd0; end assign product = a * b