| Asset | Description | |-------|-------------| | | SFQ driver, cryo‑ADC/DAC, low‑noise PLL, error‑correction micro‑kernel | | EDA support | Cadence/ Synopsys PDK with cryo‑model extensions, Spice models down to 10 mK | | Reference SoC | “Q‑Core‑A1” – a 256‑core processor with built‑in quantum control state machine | | Design‑for‑Test (DfT) | On‑die temperature sensors, noise‑monitoring probes, built‑in self‑test (BIST) for cryogenic verification |